1. Field of the Invention
This invention relates generally to a transmitter architecture. More particularly, the invention relates to variable gain amplifier systems and methods.
2. Related Art
A variable gain amplifier (VGA) is a device having a control input that can vary the gain of the device. VGAs are employed in many handheld, telephone-like communication handsets, also referred to as portable transceivers. The VGA controls gain in portable transceivers. There is a need to have accurate control over the amount of gain provided by the VGA. This is especially true for systems that do not have automatic gain adjustment to compensate for variations in a manufacturing process, ambient temperature, and/or voltage supply, or systems that have a feedback loop with a VGA in the feedback path, such as in a polar loop transmitter architecture (e.g., a transmitting architecture that conveys both phase and amplitude information during transmission).
For feedback loops with one or more VGAs in the feedback path, there are typically one or more additional VGAs in the feedforward path. For example, there may be one or more stages of VGAs implemented at baseband (BB), and one or more VGAs implemented at an intermediate frequency (IF). The IF VGA has a gain variation in a direction opposite that of the BB VGA to attempt to maintain the loop gain relatively constant. Otherwise the system will be unstable.
Two basic approaches to VGA design, or generally, design of systems using VGAs, include signal summing-VGAs (e.g., a particular topology for a VGA that sums two different current paths with two different gains) and soft-switching degeneration (e.g., the degeneration being degeneration elements comprising parallel configured, variable resistance at the emitter terminals of an amplifier, and the soft-switching including controlling the variable resistance using control voltage circuitry that operates over a continuum range of voltage values (analog) as opposed to discrete (digital) control voltage values, both of which are discussed in the following IEEE publications that are herein incorporated by reference: “A low power low noise accurate linear-in-dB variable gain amplifier with 500 MHz bandwidth,” S. Otaka, et al., IEEE J. Solid State Circuits, pp. 1942-1947, December 2000, and “Adaptive analog IF signal processor for a wide band CMOS wireless receiver,” F. Behbahani et al., IEEE J. Solid State Circuits, pp. 1205-1217, August 2001.
In the first approach (i.e., in the bulletin by S. Otaka et al.), there is a trade-off between linearity and noise mainly because the degeneration does not change with gain. In the second approach, the degeneration effected by a soft-switching degeneration configuration changes with gain (e.g., for large signals, the degeneration is large, and for small signals the degeneration is small), which facilitates achieving both linearity with respect to the input signal and low noise. However, there is gain variation (e.g., gain is not constant) over supply voltage, temperature, and manufacturing process variations. Furthermore, it is difficult to match two cascaded VGAs (e.g., VGAs disposed in the same circuit loop, with or without intervening components located between each VGA) to cancel out their gain variation.
FIGS. 1A-3 are schematic and block diagrams that provide an overview of VGA systems in a polar loop transmitter architecture that highlights some of the problems experienced in conventional VGA systems. In a typical portable transceiver device, the gain of an IF VGA is adjusted to control the output power of a power amplifier (in a manner as described below), and a BB VGA is typically used to compensate for the gain changes of the IF VGA. This combination of IF VGA and BB VGA is implemented to attempt to provide constant gain (and thus feedback loop stability) and to also avoid spectral regrowth. Note that spectral regrowth is not allowed in certain standards in wireless communications.
FIG. 1A is a simplified block diagram of a partial polar loop system 100 carrying amplitude information. Although single lines are shown as connections to the various components, it would be understood to those having ordinary skill in the art that the connections can include differential inputs. Such a partial polar loop system 100 can be part of a transmitter portion of a portable transceiver. As shown, the partial polar loop system 100 includes an error amplifier 102, a BB VGA 104, a power amplifier (PA) 106, an IF mixer 108, and an IF VGA 110. The error amplifier 102 receives a voltage, Vref, at node 112. Vref comprises varying amplitude information received from a modulator, such as an In-Phase-Quadrature (I/Q) modulator (not shown), and other processing components to be described below. The error amplifier 102 also receives a voltage, Vfb, over connection 122 from the IF VGA 110. The error amplifier 102 subtracts Vfb from Vref and provides the resulting signal (with or without gain) to the BB VGA 104 over connection 114. The output of the BB VGA 104 is input to the PA 106 over connection 116, which generates an output Vout at node 118. Vout of the PA 106 can be fed back to the IF mixer 108. The IF signal output over connection 120 is input to the IF VGA 110, which outputs a signal over connection 122 back to the error amplifier 102 to close the loop.
The closed loop gain is given by:Vout=(Vref−fb)AerrABBVGAAPAAmix  (1)where Aerr, ABBVGA, Amix, and APA are the gains of the error amplifier 102, BB VGA 104, IF mixer 108, and the PA 106, respectively. In other words, (Vref−Vfb) is amplified in the feedforward path. Further, Vfb is the output voltage (Vout) multiplied by the gain in the feedback path (which includes the gain of the IF mixer 108, represented by Amix, and the gain of the IF VGA 110, represented by AIFVGA). Thus,Vfb=VoutAIFVGAAmix  (2)
                                          V            out                                V            ref                          =                                            A              BBVGA                        ⁢                          A              PA                        ⁢                          A              err                                            1            +                                          A                BBVGA                            ⁢                              A                mix                            ⁢                              A                PA                            ⁢                              A                err                            ⁢                              A                IFVGA                                                                        (        3        )            Assuming the “1” is negligible in the denominator, the open loop gain, T, is approximated as:T=ABBVGAAPAAmixAerrAIFVGA  (4)Since the gain of the IF VGA 110 and the BB VGA 104 are inversely proportional to one another, the open loop gain is constant versus VGA gain.If T>>1, then the closed loop gain is reduced to:
                                          V            out                                V            ref                          ≅                  1                      A            IFVGA                                              (        5        )            Therefore, if the gain in the feedforward path is large, the output (Vout) is controlled by the gain in the feedback path. The output of the PA 106 is directly related to the gain (and amplitude variation) of the IF VGA 110. For example, if the IF VGA gain is large, the PA output power is small. If the IF VGA gain is small, the PA output power will be large.
For a system to be stable, it is desirable to limit open loop gain variations. To achieve this goal, compensation for IF VGA gain changes can occur through the complementary operation of the BB VGA 104. For example, IF VGA gain increases can be complemented with BB VGA gain decreases, and vice versa.
FIGS. 1B and 1C are combination schematic and block diagrams of an IF VGA 110a and a BB VGA 104a that operates in conjunction with the IF VGA 110a. The “a” signifies one embodiment for the respective IF VGA 110 and the BB VGA 104 shown in FIG. 1A. The IF VGA 110a of FIG. 1B includes differential pair transistors 124 and 126 that receive a differential input over connection 120 (FIG. 1A) at base terminals 125 and 127, respectively. At the emitter terminal of the differential pair transistors 124 and 126 is an emitter degeneration element 128 that comprises one or more n-channel MOSFETs (or NMOS transistors) functioning as a variable resistance. Degeneration elements include a resistance at the emitter or source terminals of transistors comprising the input stage of an amplifier. The resistance can include resistance from transistors and/or resistors (collectively resistive elements). Degeneration elements often improve linearity with some reduction in gain and noise. The equivalent resistance of the NMOS transistors of the emitter degeneration element 128 are changed (varied) (via soft-switching, which uses a continuous range (0-100%) of voltage values from the control voltage circuitry to create a smooth change in gain, or discrete (0 or 100%, or digital) switching to create a “stair-case” change in gain) via application of control voltage VC1 to control terminal 132. VC1 is coupled to a resistive network (not shown), and increased or decreased to provide staggered voltages to enable the equivalent resistance of one or more NMOS transistors to be changed. As the number of NMOS transistors is increased, the resulting equivalent resistance of the emitter degeneration element 128 is decreased, providing for a variation in gain.
The IF VGA 110a also includes a collector load 130 at the collector terminals of the differential pair transistors 124 and 126. The collector load 130 comprises one or more p-channel MOSFETs (or PMOS transistors) functioning as a variable resistance. The output of the collector load 130 is provided over connection 122 (FIG. 1A). The equivalent resistance of the PMOS transistors of the collector load 130 is also varied through the application of a control voltage VC2 to control terminal 134. Power is supplied via a direct current (DC) power source (not shown) providing a voltage VCC to power terminal 136, which provides a supply voltage to the differential pair transistors 124 and 126, among other components as described below.
Referring to FIG. 1C, a BB VGA 104a operates in conjunction with the IF VGA 110a to attempt to provide stable gain control. The BB VGA 104a is structured similarly to the IF VGA 110a, with differential pair transistors 138 and 140 that receive a differential input over connection 114 (FIG. 1A) at base terminals 139 and 141, respectively, an emitter degeneration element 142 comprising one or more NMOS transistors, and a collector load 146 comprising one or more PMOS transistors. Control of the emitter degeneration element 142 is via the application of a control voltage VC3 to control terminal 148. Control of the collector load 146 is via the application of a control voltage VC4 to control terminal 150. Power is supplied via a DC power source (not shown) providing a voltage VCC to power terminal 152, among other components.
The control voltages VC1 and VC2 move in the same direction (e.g., if VC1 is increasing, VC2 is increasing). The control voltages VC3 and VC4 also move in the same direction, but opposite to the control voltages VC1 and VC2 since opposite gain response is desired to provide for stable gain control.
FIGS. 2A and 2B are combination schematic and block diagrams that illustrate another approach to configuring a VGA system comprising an IF VGA 110b and a BB VGA 104b. The “b” signifies another embodiment for the respective IF VGA 110 and the BB VGA 104 shown in FIG. 1A. The IF VGA 110b comprises differential pair transistors 224 and 226 that receive a differential input over connection 120 at base terminals 225 and 227, respectively. Resistors 254 and 256 are coupled between the power terminal 136 that receives a supply voltage VCC and collector terminals of each of the differential pair transistors 224 and 226. The resistors 254 and 256 comprise a collector load. The IF VGA 110b also includes an emitter degeneration element 228 comprising one or more NMOS transistors. The emitter degeneration element 228 is controlled by the application of a control voltage VC1 to control terminal 132.
In FIG. 2B, a BB VGA 104b works in conjunction with similarly structured IF VGA 110b. The BB VGA 104b includes differential pair transistors 238 and 240 that receive an input over connection 114 (FIG. 1A) at base terminals 239 and 241, respectively, collector resistors 258 and 260 coupled to a supply voltage VCC via power terminal 152, and an emitter degeneration element 242 comprising one or more NMOS transistors controlled by the application of control voltage VC3 at control terminal 148. In this example, VC1 and VC3 move in opposite directions (i.e., as VC1 increases, VC3 decreases, and vice versa).
FIG. 3 is a schematic view of the IF VGA 110a. A similar structure can be used for the BB VGA 104a (FIG. 1C). In a typical portable transceiver system, one or more stages of an IF VGA and/or a BB VGA are implemented (e.g., cascaded, providing the same or different gains) to provide a broader gain range. An input signal is applied to differential input terminals 302 and 314 over connection 120 (FIG. 1A). Input terminal 302 is connected to the base terminal 125 of differential pair transistor 124 via connection 304. Input terminal 314 is connected to base terminal 127 of a differential pair transistor 126 via connection 316. In addition to the base terminal 125, the differential pair transistor 124 includes a collector terminal 308 and an emitter terminal 312. Similarly, the differential pair transistor 126 includes a collector terminal 320 and an emitter terminal 324, in addition to the base terminal 127.
An energy source, such as a direct current (DC) power source (not shown), supplies voltage (VCC) via power source terminal 136 to bias circuit 328, which includes a current source 329. The current source 329 of the bias circuit 328 causes current to flow through resistor 330 and resistors 332 and 334 via current source transistors 319 and 321 (which mirror the current from current source 329) to bias the base terminals 125 and 127. The base terminals 125 and 127, and the current source transistors 319 and 321 of the bias circuit 328 connected to the emitter terminals 312 and 324, are at a voltage level referenced to Vcc. The current source transistors 319 and 321 cause current to flow through the differential pair transistors 124 and 126 when properly biased, enabling the voltage appearing at the base terminals 125 and 127 to follow variations in Vcc.
The DC power applied at power source terminal 136 also supplies voltage to bias circuit 336, collector resistances 338 and 340, and to collector terminals of output transistors 342 and 348 provided in an emitter-follower configuration. The output transistors 342 and 348 are connected to output terminals 346 and 350, which provide a signal over connection 122 (FIG. 1A). The bias circuit 336, shown using a PMOS current mirror configuration as one example, provides a current supply to a collector load 130. This supply of current avoids excessive voltage drops through collector resistances 338 and 340 of the collector load 130.
The collector load 130 includes one or more parallel PMOS transistors 353 that provide a variable resistance load to the collector terminals 308 and 320 of differential pair transistors 124 and 126, respectively. The collector load 130 also includes collector resistors 338 and 340 at the collector terminals 308 and 320 of differential pair transistors 124 and 126. Resistance of the collector load 130 is varied based on varying VC2 applied at control terminal 134. VC2 is coupled to the collector load 130 via a resistive network 354. The equivalent resistance of the collector load 130 is changed by operating the PMOS transistors 353 of the collector load 130 on and off (in either a soft-switching manner or discrete (digital) manner). For example, with all of the PMOS transistors 353 of the collector load 130 off, the resistance on the collector side of the differential pair transistors 124 and 126 is due to the collector resistors 338 and 340. Turning the PMOS transistors 353 on provides for a reduced equivalent resistance of the combined collector resistors 338 and 340 and the balance of the collector load 130.
The emitter degeneration element 128 is included at the emitter terminals 312 and 324. The emitter degeneration element comprises a resistor 360 connected in parallel with one or more NMOS transistors 359. The NMOS transistors 359 of the emitter degeneration element 128 are shown connected in series with two other resistors 361 and 363 at the source and drain terminals of each of the NMOS transistors 359. Resistors 361 and 363 reduce the effect in total resistance resulting from changes in variable resistance of the NMOS transistors 359. Similar to the PMOS transistors 353 of the collector load 130, the equivalent resistance of the NMOS transistors 359 of the emitter degeneration element 128 is varied through the coupling of VC1, applied at control terminal 132, to the emitter degeneration element 128 via a resistive network 362. For example, when VC1 applied to the control terminal 132 is low, all of the NMOS transistors 359 of the emitter degeneration element 128 are off, resulting in the resistance at the emitter terminals 312 and 324 being provided predominantly by the resistor 360. If VC1 applied to the control terminal 132 is high, one or more of the NMOS transistors 359 begin to turn on, resulting in a parallel combination of the resistor 360 with the activated NMOS transistors 359 and associated resistors 361 and 363, reducing the total resistive load at the emitter terminals 312 and 324.
The control operation described above that varies the equivalent resistance of the collector load 130 and the emitter degeneration element 128 is accomplished to provide linear-in-dB gain control (e.g., voltage gain of the differential pair transistors 124 and 126 in decibels=20 log|voltage gain expressed as a ratio of voltage over voltage |dB). The gain of the IF VGA 110a is determined by the total resistive load on the collectors of the differential pair transistors 124 and 126, divided by the total resistive load on the emitters of the differential pair transistors 124 and 126. Generally, if the inherent emitter resistance of the differential pair transistors 124 and 126 is neglected, the gain of the IF VGA 110a is approximately the collector load 130 comprising the PMOS transistors 353 in parallel with the collector resistances 338 and 340, divided by the emitter degeneration element 128 (comprising the resistor 360 in parallel with the combination of NMOS transistors 359 and series resistors 361 and 363). Thus, if a gain increase is desired, the total collector resistive load is increased and/or the total emitter resistive load is decreased. To decrease the gain of the IF VGA 110a, the total collector resistive load is decreased and/or the total emitter resistive load is increased.
Although the NMOS transistors 359 of the emitter degeneration element 128 are shown in series with resistors 361 and 363, and the PMOS transistors 353 of the collector load 130 have no such combination at the source and drain terminals of each of the PMOS transistors 353, one skilled in the art would understand that a series resistance could be used with or without either PMOS transistors 353 and the NMOS transistors 359. For example, a designer may choose to include a series resistance with the PMOS transistors 353 of the collector load 130 to achieve a variable resistance with less dependence on the resistivity of the transistor itself.
One problem with the IF VGA 110a described above, alone or in combination with other VGAs (e.g., BB VGA(s), IF VGA(s)) similarly structured to the configuration of the IF VGA 110a, is that the overall gain is difficult to control when the characteristics of the circuit dynamically change as a result of changes in supply voltage, ambient temperature, and/or manufacturing process. Thus, a goal of many designers is to provide an overall gain (e.g., resulting from the IF VGA 110a and BB VGA 104a combination) that is relatively constant (e.g., within a small margin of variation).
FIGS. 4A and 4B are graphs that illustrate some of the problems with conventional VGA systems, such as the VGA system 110a depicted in FIG. 3. FIG. 4A shows simulated variations in gain due to changes in supply voltage (e.g., 2.7V to 3.3V in 0.1V increments) of a combined circuit using an IF VGA and a BB VGA similarly structured to the VGA 110a shown in FIG. 3. FIG. 4B shows the total gain variation resulting from the combination of the IF VGA and BB VGA corresponding to the graph in FIG. 4A. In FIG. 4A, the graph includes an x-axis corresponding to a differential input control voltage and a y-axis corresponding to gain in units of decibels (dB). Curves 402 starting at approximately 50 dB and ending at −10 dB correspond to gain for an IF VGA. Each curve of curves 402 of the IF VGA corresponds to changes in gain as a result of variations in power source supply voltage, as indicated by the symbols with corresponding Vcc values shown in a symbol ledger 405. The IF VGA output level decreases with increases in differential input control voltage (e.g., a voltage used to generate VC1 and VC2 (FIG. 1B)) and varies with variations in supply voltage, but with marked distinction for each curve due to supply variations that would be further exacerbated by changes in ambient temperature and/or manufacturing process. This can be problematic in that with decreasing supply voltage, the differential input control voltage must be decreased to maintain a constant power level output.
The curves labeled 404 show increasing gain with an increase in differential input control voltage, and correspond to changes in power source supply voltage (again, further exacerbated if the BB VGAs are subject to variations in manufacturing process and/or ambient temperature). The BB VGA curves 404 have a range of approximately 30 dB down to −30 to −35 dB over the range in differential input control voltage. One goal in the design of VGA systems is to keep the combined gain variation of the IF VGA and BB VGA within a limited range. FIG. 4B shows the simulated, combined gain variation curves 406 for the IF VGA and BB VGA used to develop the curves 402 and 404 shown in FIG. 4A. The combined gain variation curves 406 range anywhere from 31 dB down to 16 dB. Even within the desired linear operating range shown between points A and B, the variation in output power as a result of changes in supply voltage (e.g., VCC) for a given differential input control voltage is significant.
Therefore, it would be desirable to provide a VGA system for control of a power amplifier that exhibits limited variation in gain while tolerating changes in supply voltage, ambient temperature, and/or manufacturing process.